A controller for a double data rate (DDR) memory device must meet certain timing requirements. Such requirements are currently specified in two standards of the JEDEC Solid State Technology Association (once known as the Joint Electron Device Engineering Council). These are: JEDEC standard JESD79 (“Double Data Rate (DDR) SDRAM Specification”) and JEDEC standard JESD209 (“Low Power Double Data Rate (DDR) SDRAM Specification”), available from www.jedec.org.
Of the timing requirements, the two most problematic are as follows.
The first is meeting the setup and hold requirements of the (double-rate) data to be written to the memory (e.g. tDS and tDH in the above JEDEC standards). Ideally a timing offset should be generated between the write strobe and the DDR write data (e.g. the DQS write strobe in the above JEDEC standards).
The second is sampling the (double-rate) read data returning from the DDR chip using the ‘strobe’ signals which transition at very nearly the same time as the data. Ideally a timing delay should be added to the incoming read strobe before using it to sample the DDR data (e.g. the DQS read strobe in the above JEDEC standards).
A timing offset on the DQS write strobe can be achieved by using a double-rate internal clock (or a two-phase, single rate internal clock with a quarter cycle offset). However, guaranteeing the availability of such an internal clock comes at a cost (a clock running at some even multiple of the memory clock must exist).
The delay for the DQS read strobe can be generated by contriving a tuneable delay circuit (the same circuit can then also be used to offset the write data with respect to the DQS write strobe. However, the mechanism by which this delay is tuned (usually a Phase-Locked-Loop or a Delay-Locked-Loop) requires careful design.